[Dart-dev] [5504] DART/branches/development/adaptive_inflate/fill_inflation_restart. html: Added some notes pointing out that when you run this tool

nancy at ucar.edu nancy at ucar.edu
Thu Jan 12 14:29:19 MST 2012

Revision: 5504
Author:   nancy
Date:     2012-01-12 14:29:19 -0700 (Thu, 12 Jan 2012)
Log Message:
Added some notes pointing out that when you run this tool
it's going to need anything the model_mod needs to start
up, which might include netcdf data/grid files, and namelist
settings much match those used for the assimilation run
if the contents of the state vector is controlled by settings
in the model_nml namelist.

Modified Paths:

-------------- next part --------------
Modified: DART/branches/development/adaptive_inflate/fill_inflation_restart.html
--- DART/branches/development/adaptive_inflate/fill_inflation_restart.html	2012-01-12 20:27:43 UTC (rev 5503)
+++ DART/branches/development/adaptive_inflate/fill_inflation_restart.html	2012-01-12 21:29:19 UTC (rev 5504)
@@ -48,6 +48,24 @@
 The program reads 2 real values from the console and always
 writes out a file called "inflate_ics", which can be renamed
 to match the input inflation restart file in the filter namelist.
+Note that if the model you're working with requires any files
+to be present in the current directory at assimilation time
+(e.g. CAM and WRF require netcdf file(s) that define the size 
+of the grid) or if the contents of the state vector are 
+settable by namelist, then all these things must be set 
+and files must be present in the current directory when
+you run this tool.  The size of the inflation restart file
+must match exactly the size of the state vector that will
+be used in the assimilation run.
+Also note that the output is a binary file and should be created
+on the same platform type as your assimilation run will be done.
+You can't move binary files between processors with different
+processor types if one uses little-endian byte order and the
+other uses big-endian.  The most common incompatible pairing these
+days is between IBM Power chips that are big-endian and Intel chips 
+that are little-endian.

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